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| as8515 data acquisition system with power management and lin transceiver for 12v battery sensor applications www.ams.com revision 0.7 1 - 65 1 general description the as8515 is designed for simultaneous measurement of shunt current sensor signal and battery voltage by two independent adc channels. both channels can measure small signals up to 219 mv versus ground through programmable gain amplifier or larger signals in the 1v range without amplifier. after analog to digital conversion and digital filtering, the resulting digital values are accessible through 4-wire serial interface. the device is powered directly from the battery through ldo and provides a 3.3v supply for an external microcontroller. for communication with the next level ecu, the device offers a lin 2.1 transceiver. measurement of battery voltage is supported through resistive attenuator with disable for power saving in standby. the device is a stacked die system providing a high voltage cmos ic for power management and transceiver functions as a top die and low voltage sensor interface functions as a bottom die inside a 32-pin mlf (5x5 mm) package. 2 key features ?? a precision voltage attenuator with power down facility ?? lin 2.1 transceiver ?? power-on reset with programmable reset timeout and brown- out detection through factory setting ?? a window watchdog function in the normal mode and a timeout watchdog in the device standby mode as a factory option ?? load dump protection (42v) for all battery supplied pins and enable pin ?? internal reverse polarity protection (up to -27v) for all battery- sensing pins, and lin bus pin ?? over temperature warning & shutdown functions ?? two independent high resolution a/d converters with programmable over sampling ratio ?? programmable sampling rate up to 4khz throughput ?? programmable gain, low noise amplifier for current channel with gain stages 5, 25, 40, 100 ?? internal temperature sensor ?? synchronous acquisition for both adc channels ?? reference-voltage source (high precision and high stability) ?? offset auto zero architecture on both channels ?? current monitoring comparator with interrupt signal generation and c clock enable. timer with 2 related outputs for single shot sampling of current and voltage channel in low power mode. ?? precision on chip rc oscillator or external clock. low slew, low emc clock output which can be used by external microcontroller which is enabled respectively disabled by mode control through spi and interrupt from current monitor in low power mode. the integrated circuit can execute measurements with internal and external sensors and sources for the voltage channel and with external sensor for the current channel. external sensors: ?? current measurement via shunt resistor (4 ranges) ?? battery voltage (internal voltage divider to battery) ?? etr and ets for external temperature sensor (with switchable current source) internal sensors: ?? on chip temperature sensor ?? internal current sources for functional test of measurement path and the connection of shunt resistor 3 applications the as8515 is suitable for battery sensors, having shunt current sensor at minus pole. for lead acid, li-ion batteries up to 18v nominal, 42v over voltage capability. the device is also ideal as a general purpose sensor interface for automotive lin slaves.
www.ams.com revision 0.7 2 - 65 as8515 datasheet - applications figure 1. as8515 block diagram ldo lin spi, diagnosis, wwd tx rx en sclk cst csb reset dvdd avdd vref men vcm rshh rshl vsense_gnd dvss low precision clock high precision clock hp_clk lp_clk lpm control logic clk voltage channel adc current channel adc int voltage channel multiplexer, current source to voltage channel adc vsense vsup spi, comparator, filter option etr ets avss lin reference generator vcc vsense_in chop_clk vss por_vcc por_vsup temperature limiter pga dec pga dec sdi sdo as8515 www.ams.com revision 0.7 3 - 65 as8515 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 5 4.1 pin descriptions.......................................................................................................... .......................................................................... 5 5 absolute maximum ratings .................................................................................................... .................................................. 7 6 electrical characteristics.................................................................................................. ......................................................... 8 6.1 operating conditions...................................................................................................... ...................................................................... 8 6.2 dc/ac characteristics for digital inputs and outputs ...................................................................... .................................................... 8 6.3 system specifications ..................................................................................................... ................................................................... 10 7 as8515 top die overview..................................................................................................... ................................................. 11 7.1 voltage attenuator ........................................................................................................ ...................................................................... 11 7.2 voltage regulators (ldo) .................................................................................................. ................................................................ 11 7.3 lin transceiver ........................................................................................................... ....................................................................... 11 7.4 temperature monitor/limiter............................................................................................... ................................................................ 11 7.5 vsup under-voltage reset.................................................................................................. .............................................................. 12 7.6 reset ..................................................................................................................... ............................................................................. 12 7.7 vcc under-voltage reset ................................................................................................... ............................................................... 12 7.8 window watchdog (wwd) ..................................................................................................... ............................................................ 13 7.9 timeout watchdog (twd) .................................................................................................... .............................................................. 13 7.10 modes of operation ....................................................................................................... ................................................................... 14 7.10.1 normal mode ............................................................................................................ ............................................................... 15 7.10.2 standby mode........................................................................................................... ............................................................... 15 7.10.3 temporary shutdown mode ................................................................................................ .................................................... 15 7.10.4 thermal shutdown mode.................................................................................................. ....................................................... 15 7.11 initialization ........................................................................................................... ............................................................................ 16 7.12 wake-up .................................................................................................................. ......................................................................... 17 7.12.1 remote wake-up event................................................................................................... ........................................................ 17 7.13 lin bus transceiver...................................................................................................... .................................................................. 18 7.13.1 transmit mode.......................................................................................................... ............................................................... 18 7.13.2 receive mode........................................................................................................... ............................................................... 18 7.14 rx and tx interface ...................................................................................................... .................................................................... 19 7.14.1 input tx............................................................................................................... ..................................................................... 19 7.14.2 output rx.............................................................................................................. ................................................................... 19 7.15 mode input en............................................................................................................ .................................................................... 20 7.16 top die block specifications ............................................................................................. ............................................................... 21 7.16.1 voltage attenuator ..................................................................................................... .............................................................. 21 7.16.2 voltage regulator (ldo) ................................................................................................ ......................................................... 22 7.16.3 vcc power-on-reset ..................................................................................................... ......................................................... 22 7.16.4 vsup power-on-reset .................................................................................................... ........................................................ 22 7.16.5 window watchdog timer.................................................................................................. ....................................................... 23 7.16.6 lin transceiver ........................................................................................................ ............................................................... 23 7.17 timing diagrams .......................................................................................................... .................................................................... 24 www.ams.com revision 0.7 4 - 65 as8515 datasheet - contents 7.17.1 tx timeout watchdog.................................................................................................... .......................................................... 26 7.17.2 temperature limiter .................................................................................................... ............................................................ 26 7.18 top die registers ........................................................................................................ ..................................................................... 26 8 as8515 bottom die overview .................................................................................................. .............................................. 28 8.1 current measurement channel ............................................................................................... ........................................................... 28 8.2 voltage/temperature measurement channel ................................................................................... .................................................. 28 8.3 digital implementation of measurement path................................................................................ ..................................................... 29 8.4 reference-voltage......................................................................................................... ..................................................................... 29 8.5 oscillators............................................................................................................... ............................................................................ 29 8.6 power-on reset ............................................................................................................ ..................................................................... 29 8.7 modes of operation ........................................................................................................ .................................................................... 30 8.7.1 normal mode 1 (nom1) .................................................................................................... ........................................................ 31 8.7.2 normal mode 2 (nom2) .................................................................................................... ........................................................ 31 8.7.3 standby mode1 (sbm1) .................................................................................................... ........................................................ 32 8.7.4 standby mode2 (sbm2) .................................................................................................... ........................................................ 33 8.8 initialization sequence at power on ....................................................................................... ........................................................... 33 8.8.1 soft-reset of device using bit d[7] of reset register 0x09.............................................................. ......................................... 34 8.8.2 soft-reset of the measurement path using bit d[7] of reset register 0x09 ................................................ ............................. 35 8.8.3 reconfiguring gain setting of pga ...................................................................................... .................................................... 35 8.8.4 configuring the device during normal mode ............................................................................... ............................................. 35 8.8.5 standby mode - power consumption ........................................................................................ ................................................ 36 8.9 bottom die block specifications........................................................................................... .............................................................. 36 8.9.1 current measurement ranges (across 100 (5%) shunt resistor) ...................................................................................... 36 8.9.2 system specifications................................................................................................... ............................................................. 43 9 4-wire spi interface........................................................................................................ ........................................................ 44 9.1 spi timing parameters ..................................................................................................... ................................................................. 44 9.1.1 spi frame............................................................................................................... ................................................................... 45 9.1.2 write command........................................................................................................... .............................................................. 45 9.1.3 read command............................................................................................................ ............................................................. 46 9.1.4 timing .................................................................................................................. ...................................................................... 47 9.2 bottom die registers...................................................................................................... .................................................................... 48 10 application information .................................................................................................... ..................................................... 60 11 package drawings and markings.............................................................................................. ............................................ 61 12 ordering information....................................................................................................... ...................................................... 64 www.ams.com revision 0.7 5 - 65 as8515 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin name pin number pin type description rshl 1 analog input negative differential input for current channel vref 2 analog output internal reference voltage to sigma delta adc; connect 100nf to a vss from this pin. vcm 3 analog output common mode voltage to the internal measurement path; connect 100nf to a vss from this pin. avdd 1 4 analog input +3.3v power-supply; supplied by ldo output (vcc) in top die ; should be shorted to pin 21 (vcc) externally. avss 2 5 power supply 0v power-supply ground analog dvdd dvss sdo sclk csb sdi clk int cst tx rx reset rshh rshl vref vcm avdd avss etr ets vsense_in vsense_gnd vss vsup lin en men vsense chop_clk as8515 vcc 18 20 17 23 24 21 19 22 7 6 5 8 3 2 1 4 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 www.ams.com revision 0.7 6 - 65 as8515 datasheet - pin assignments etr 6 analog input voltage channel single ended input ets 7 vsense_in 8 analog i/o battery voltage attenuator output and voltage channel input vsense_gnd 9 analog input input signal for voltage channel (low) lin 10 analog i/o lin bus vss 2 11 power supply 0v power-supply ground analog vsense 12 analog input battery voltage input connect 100nf to vss from this pin. vsup 13 power supply supply input from battery (through external reverse polarity protection device) -14- - vcc 1 15 analog output regulated 3.3v output supply for loads up to 50ma csb 16 digital input chip select for bottom die sclk 17 digital input clock signal spi sdo 18 digital output data signal sdo dvss 2 19 power supply 0v power-supply digital dvdd 1 20 analog input +3.3v power-supply; supplied by ldo output (vcc) in top die ; should be shorted to pin 21(vcc) externally. chop_clk 21 digital output chopper clock men 22 digital i/o digital output for bottom die in sbm mode 3 and input for top die sdi 23 digital input data signal sdi clk 24 digital i/o internal/external digital clock signal -25- - int 26 digital output interrupt not: wake-up, digital interrupt, ready flag 2 cst 27 digital input chip select for top die tx 28 digital input lin transceiver transmit pin rx 29 digital output lin transceiver receive pin reset 30 digital output reset output (open drain) en 31 digital input enable input rshh 32 analog input positive differential input for current channel 1. pin #4, pin #20 and pin #15 needs to be shorted externally on the board. pin #21 is the ldo output that supplies pin #4 and p in #20. 2. pin #5, pin #11 and pin #19 needs to be shorted externally on the board as they are the grounds. 3. use as output port only. table 1. pin descriptions pin name pin number pin type description www.ams.com revision 0.7 7 - 65 as8515 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 8 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min typ max units comments electrical parameters vsup supply voltages -0.3 42 v vsense battery voltage inputs -27 42 v avdd, dvdd dc supply voltage -0.3 5 v en enable input -0.3 42 v vcc regulated output supplies -0.3 5 v vcc generated by top die must not be larger than 5v on board level as it has to be connected with bottom die avdd and avcc lin lin bus -27 40 v analog & digital inputs and outputs -0.3 5 v input current (latch-up immunity) -100 100 ma norm: aec-q100-004 electrostatic discharge esd electrostatic discharge norm: aec-q100-002 6 kv lin, vss 4 kv vsup, vsense 2 kv all other pins continuous power dissipation p tot 1 1. total power dissipation cannot exceed 0.375w to avoid increase in junction temperature, i.e. greater than 130oc. vcc ldo can supply current externally, which is not greater than 17ma at 18v vsup and 20ma at 16v vsup. total operating power dissipation (all supplies and outputs) 0.375 w mlf-32 in still air, soldered on jedec standard board @125o ambient, static operation = no time limit temperature ranges and storage conditions r package thermal resistance 34 40 oc/w t stg storage temperature -55 150 oc t j junction temperature 130 oc t body package body temperature 260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % msl moisture sensitive level 3 represents a maximum floor time of 168h www.ams.com revision 0.7 8 - 65 as8515 datasheet - electrical characteristics 6 electrical characteristics unless otherwise noted in this specification, all defined toler ances of parameters are assured over the whole operation conditi ons range and also over lifetime. 6.1 operating conditions 6.2 dc/ac characteristics for digital inputs and outputs all pull-up, pull-downs have been implemented with active devices. sdo have been measured with 10pf load. int output. cst, csb, txd. table 3. operating conditions symbol parameter min typ max unit note v sup supply voltages 4.3 18 v v sense battery voltage input 4.5 18 v avdd positive supply voltage 3.15 3.45 v avss negative supply voltage 0 v dvdd positive digital su pply voltage 3.15 3.45 v referring to dvss, typical 10% dvss negative digital supply voltage 0 v lin lin bus 0 18 v en enable input 0 18 v vcc regulated output supply 3.15 3.45 v t amb ambient temperature -40 115 oc maximum junction temperature (t j ) is 130oc i sup 1 1. total power dissipation cannot exceed 0.375w to avoid increase in junction temperature, i.e. greater than 130oc. vcc ldo can supply current externally, which is not greater than 17ma at 18v vsup and 20ma at 16v vsup. supply current 27 ma f clk system clock frequency 8.192 mhz when external clock is selected, internal clock will be 4.096 mhz table 4. int symbol parameter condition min typ max unit v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 4 ma table 5. cst, csb symbol parameter condition min typ max unit v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current -1 +1 a i pu pull-up current pulled to gnd -150 -10 a www.ams.com revision 0.7 9 - 65 as8515 datasheet - electrical characteristics sdi, sclk. sdo output. chop_clk output. en input. clk i/o. table 6. sdi, sclk symbol parameter condition min typ max unit v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current -1 +1 a table 7. sdo symbol parameter condition min typ max unit v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 4 ma table 8. chop_clk symbol parameter conditions min typ max units v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 4 ma table 9. en symbol parameter conditions min typ max units v ih high level input voltage 0.8*vcc v v il low level input voltage 0.2*vcc v i leak input leakage current en = vss -1 +1 a i pd_en pull-down current pulled up to vcc 30 100 a table 10. clk i/o symbol parameter condition min typ max unit v ih high level input voltage 2.4 v v il low level input voltage 1 v i leak input leakage current -1 +1 a i pd_en pull-down current 10 100 a i o output current 4 ma v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v www.ams.com revision 0.7 10 - 65 as8515 datasheet - electrical characteristics men output. rx output. reset output. 6.3 system specifications note: stand by mode power consumption is sum of stop mode power consumption and average of normal mode power consumption over a period of 2s (nom1 time of device is low in standby mode). table 11. men symbol parameter conditions min typ max units v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 2 ma table 12. rx symbol parameter conditions min typ max units v oh high level output voltage vcc-0.5 v v ol low level output voltage vss+0.4 v i o output current 1 ma i pu_reset pull-up current pulled down to vss -30 -100 a table 13. reset symbol parameter conditions min typ max units v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current open drain pull-down 8 ma table 14. system specifications symbol parameter condition min typ max unit ivsupnom current consumption in normal mode no load on vcc, lin bus in dominant state 7ma ivsupstdby current consumption standby no load on vcc, lin bus in recessive state 80 a www.ams.com revision 0.7 11 - 65 as8515 datasheet - as8515 top die overview 7 as8515 top die overview the as8515 top die consists of a resistive divider, a low dropout regulator, and a lin bus transceiver. additionally integrated are a reset unit with a power-on-reset delay, programmable window watchdog and timeout watchdog timers as a factory programming option. it also includes a watchdog timeout on lin tx node to indicate if the microcontroller is stuck in a loop and the lin bus remains in dominant time for more than the necessary time. 7.1 voltage attenuator a resistive divider is used as a battery voltage attenuator. like the amplifier, the attenuator can be enabled or disabled thro ugh spi, and in the device standby mode, we additionally need logic high on men pin for enabling. internal reverse polarity protection is provided for vsense pin. figure 3. attenuator implementation 7.2 voltage regulators (ldo) the device has a low-dropout voltage regulator named ldo, 3.3v volt age outputs. the output of the ldo is vcc. the regulator is always on except when the device enters the over-temperature shutdown. the regulator has in-built short-circuit current limitation feature. the regulator can be temporarily shut down for hard reset of the external circuitry by configuring the device to temporary shutdown mode through spi. the ldo power-up happens when the por-vsup event occurs (reset_vsup_ n switching from low to high). the ldo will be switched off if there is an under vo ltage on vcc, that is, when r eset_vcc_n switches back to low. 7.3 lin transceiver the device has a lin transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the lin bus . further, the slew rate is independent of the bus load. the transmitter relays the data from the lin controller (tx pin) to the bus (lin pin), and the receiver provides the data on the bus to the controller (rx pin). the transceiver conforms to the lin 2.1 standard. the lin transceiver has a timeout watchdog for tx. after the timeout, the lin bus will be released to the recessive state from the dominant state. the bus driver has an in-built short-circuit current limitation facility to protect the device from damage when there is a shor t between the bus and the supply. in addition to the data receiver, there is a low-power receiver active in the device standby mode which received a wake-up event from the lin bus to bring the device to normal mode. 7.4 temperature monitor/limiter the temperature limiter circuit powers down the device when the junc tion temperature exceeds 170c (nominal). it also issues an over- temperature warning at 160c (nominal). the device is powered up again when the junction temperature falls below 140c (nominal ). the over- temperature warning flag is also cleared at this temperature. the temperature limiter circuit can be optionally disabled through spi. v sense vsense_in vsense_gnd pd www.ams.com revision 0.7 12 - 65 as8515 datasheet - as8515 top die overview 7.5 vsup under-voltage reset when vsup drops below vsuvr_on, the reset_vsu p_n switches back to low level. this is treated as a master reset and will have th e highest priority over all other signals. in this case, the regulators, lin transceiver, and all other blocks are shut off, and the device comes to a complete stop. the device returns to the normal mode when vsup ri ses over vsuvr_off again irrespective of the mode it was in pr ior to this under-voltage condition. 7.6 reset reset module generates an active-low reset signal for the extern al circuitry supplied by vcc. the behavior of the reset output is depicted in figure 4 in different cases. as shown, reset signa l is affected by an under-v oltage condition on vcc and wa tchdogs which are described in detail in the subsequent sections. the reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms. figure 4. reset functionality 7.7 vcc under-voltage reset when vcc drops below vuvr_on, the reset_vcc_n switches back to low level. this event generates a reset output. the reset output is released again only a reset period (t res ) later after vcc rises above vuvr_off. if the time difference between the vcc falling below vuvr_on and rising above vuvr_off is less than t rr , there will be no reset output. the reset output is affected in the conditions like over-temperature shutdown and temporary shutdown only through vcc under voltage. vcc vsup vuvr_off t res t rr t>tj t www.ams.com revision 0.7 14 - 65 as8515 datasheet - as8515 top die overview 7.10 modes of operation the as8515 top die provides the following four main operating modes: ?? normal mode ?? standby mode ?? temporary shutdown mode ?? thermal shutdown mode the lin transceiver can be programmed to operate with lower slew in the normal mode. see figure 6 for a detailed state transition diagram. soft states like ?txwd wait?, ?standby wait?, and other wait states have also been included in the state diagram for completeness. figure 6. finite state machine model of as8515 top die reset timeout otp load wait_test wait_otp temp shut standby por_vsup otp_load rx=0 test_en temp shutdown o t p _ e n temp170 temp170 ! temp170 s t a n d b y & ~ o t p _ m o d e standby & otp_mode r w a k e _ w a i t / l o c a l _ w a i t 128msec ! por_vcc || stdby_timeout reset timeout t e m p s h u t d o w n ! por_vcc || wwdtimeout standby wait txwd_timeout temp170 ! s t a n d b y t e m p s h u t d o w n tx=1 t e m p s h u t d o w n temp170 temp170 ! por_vcc || stdby_timeout r x = 0 temp170 ! por_vcc || wwdtimeout rwake / local wake init0 ovtemp normal txwd wait www.ams.com revision 0.7 15 - 65 as8515 datasheet - as8515 top die overview note: l = low state, h = high state, ot = over temperature reset, u vcc = under-voltage vcc, u vsense = under-voltage vsense, rwake = remote wake, x = don?t care. 7.10.1 normal mode this is the mode after the power-up. in this mode, voltage regulator, lin transceiver, window watchdog is all active. the resis tive divider can be enabled through spi. lin transceiver is capable of sending the tx data from microcontroller to the lin bus at a maximum rate of 20kbps. 7.10.2 standby mode standby mode is a functional low power mode and is entered by pulling en to ground. the lin transceiver, resistive divider, win dow watchdog, and tx timeout watchdog circuits are disabled. but, it is possible to selectively enable the voltage and current measurement pa ths in this mode using an externally generated measurement enable (men) signal on the men pin. the timeout watchdog can be enabled in this mode to make sure that the microcontroller is active. 7.10.3 temporary shutdown mode in this mode, the regulator is powered down and the vcc is pulled down. this provides an alternative way to reset those compone nts powered by as8515. the feature has to be enabled by the factory programming option and can be invoked through spi. the lin transceiver along with the lin wake-up circuits are powered down. no remote wake functionality possible. lin bus enters into recessive state. the syst em goes out of this mode to normal mode after the timeout of an internal timer. 7.10.4 thermal shutdown mode if the junction temperature t j is higher than t sd , the device will be switched into the thermal shutdown mode. the regulator and the transceiver are completely disabled. only the over-temperature monitor is active. as soon as the temperature returns back to t ret , the system enters normal mode. table 15. transition table transition interface reg. 0x05 d0 flags comments from mode to mode lin rx tx en rwake u vsense ot u vcc normal mode stand-by x-rs x-h 1 1. effect of transition h 2 2. cause for transition h-l 2 l x x inactive inactive tx is high for t stndy_trigger temporary shutdown x-rs x-h 1 xh h 2 x x inactive set the control bit is set through the 4-wire spi interface over- temperature x-rs x-h 1 xx l x x set set temperature monitor output asserted (covered by scan) standby mode normal (lw) x h-x 1 x l-h 2 l x x inactive inactive normal (rw) x h-x 1 h x l set x inactive inactive remote wake up event occurred on lin temporary shutdown rs h 1 h l h 2 x x inactive set the control bit is set through the 4-wire spi interface over- temperature rs h 1 hl l x x set set temperature monitor output asserted (covered by scan) temporary shutdown mode normal rs-x h-x 1 x x l x x inactive clear internal 128ms timer expired over- temperature mode normal rs-x h-x 1 x x l x x clear clear temperature monitor output de-asserted (covered by scan) all states power off x x x x x x l-h 2 xx www.ams.com revision 0.7 16 - 65 as8515 datasheet - as8515 top die overview 7.11 initialization when the power supply is switched on, when vsup > vsuvr_off, reset_vsup_n beco mes high. this starts the regulator ldo with 3.3v and vuvr_off option of 2.75v. when vcc > vuvr_off (2.75v), ac tive-low porn_2_otp is generated. the rising edge of porn_2_otp lo ads contents of fuse onto the factory setting latch after load access time t load . load_otp_in_prereg signal loads contents of factory setting latch onto a register. this register provides the actual settings of ldo, vuvr_off and reset timeout period t res . this is done as the factory setting block is powered by the vcc. if vc c > vuvr_off (phase 2), reset timeout is restarted. reset signal is de-asserted after reset timeout period t res (phase 2) and then device enters into normal mode. the circuit also needs to initialize correctly for very slow ramp rates on vsup (of the order of 0.5v/min). figure 7. initialization sequence table 16. vsup>vsuvr_on and vcc www.ams.com revision 0.7 18 - 65 as8515 datasheet - as8515 top die overview 7.13 lin bus transceiver the as8515 has an integrated bi-directional bus interface device for data transfer between lin bus and the lin protocol control ler. the transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage c omparator followed by a de-bouncing unit. 7.13.1 transmit mode during transmission the data at the pin tx will be transferred to the bus driver to generate a bus signal. to minimize the elec tromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave shaping unit. transmitting will be interrupted in the following cases: ?? thermal shutdown active ?? master reset (vsup < vsuvr_on) the recessive bus level is generated from the integrated 30k pull up resistor in serial with an active diode this diode prevent s the reverse current of vbus during differential voltage between vsup and bus (vbus>vsup). no additional termination resistor is necessary t o use the as8515 in lin slave nodes. if this ic is used for lin master nodes it is necessary that the bus pin is terminated via an extern al 1k resistor in series with a diode to vsense. 7.13.2 receive mode the data signals from the bus pin will be transferred continuously to the pin rx. short spikes on the bus signal are suppressed by the implemented debouncing circuit. including all tolerances the lin specific receive threshold values of 0.4*vsup and 0.6*vsup wil l be securely observed. figure 9. receive mode impulse diagram t < t deb_bus t < t deb_bus rx bus 40% 50% 60% v thr_max v thr_min v thr_hys v thr_cnt www.ams.com revision 0.7 19 - 65 as8515 datasheet - as8515 top die overview 7.14 rx and tx interface 7.14.1 input tx the 3.3v input tx controls directly the bus level. lin transmitter acts like a slew-controlled level shifter. a dominant state (low) on tx leads to the lin bus being pulled low (dominant state) too. the tx pin has an internal active pull up connected to vcc. this guarantees that an open tx pin generates a recessive bus level. figure 10. tx interface 7.14.2 output rx the received bus signal will be output to the rx pin: bus < vthr_cnt ? 0.5 * vthr_hys rx = low bus > vthr_cnt + 0.5 * vthr_hys rx = high this output is a push-pull driver between vcc and gnd with an output current of 1ma figure 11. rx interface vcc tx as8515 mcu vcc i pu_txd rc-filter (10ns) rx vcc as8515 mcu www.ams.com revision 0.7 20 - 65 as8515 datasheet - as8515 top die overview 7.15 mode input en the as8515 top die is switched from normal mode to the standby mode with a falling edge on en and keeping tx high for t stndy_trigger time. device is switched from standby mode to normal mode with a rising edge at the en pin. the mode change for top die with a falling edge on en can be done independently from the state of the transceiver bus. this ensures the direct control of device to enter into standb y mode by microcontroller using en pin. figure 12. en pin functionality the en input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. figure 13. enable interface if the application doesn?t need the low-power modes of the device, a direct connection of en to vcc is possible. in this case t he top die operates in permanent normal mode. also possible is the external (outside of the module) control of the en line via vsup signal as shown below. en tx normal mode normal mode standby/sleep mode t tx_su t tx_hd t stndy_trigger + + vcc reset tx rx en vsup lin vss as8515 mcu +3.3v c load v bat c in vsense www.ams.com revision 0.7 21 - 65 as8515 datasheet - as8515 top die overview figure 14. en connection for permanent normal mode 7.16 top die bloc k specifications this section provides specification of design related key parameters. 7.16.1 voltage attenuator table 18. voltage attenuator symbol parameter condition min typ max unit rdiv division ratio 21 v/v vsense input voltage range/ battery voltage range 4.5 12 18 v p,rdiv ratio error at room temperature, vsense=12v 1 % dt1,rdiv ratio drift (with reference to temperature) temperature: -25 to +65o @vsense=12v maximum values will be added after device evaluation (to be guaranteed by evaluation) 0.05 % dt2,rdiv temperature: -40 to +125o @vsense=12v maximum values will be added after device evaluation (to be guaranteed by evaluation) 0.2 dv1,rdiv ratio drift (with reference to vsense) vsense: 11v to 13v @temperature=27o maximum values will be added after device evaluation (to be guaranteed by evaluation) 0.05 % dv2,rdiv vsense: 6v to 18v @temperature=27o maximum values will be added after device evaluation (to be guaranteed by evaluation) 0.2 + + vcc reset tx rx en vsup lin vss as8515 mcu +3.3v c load v bat c in www.ams.com revision 0.7 22 - 65 as8515 datasheet - as8515 top die overview 7.16.2 voltage regulator (ldo) 7.16.3 vcc power-on-reset 7.16.4 vsup power-on-reset table 19. voltage regulator symbol parameter condition min typ max unit v sup input supply voltage 4.3 12 18 v vcc output voltage range 3.15 3.3 3.45 v i load ldo load current 45 ma icc_sh output short circuit current normal mode 250 ma dvcc1 line regulation vcc / vsup for vsup range 8 mv/v loreg load regulation vcc / iccn (0.5ma < i load < 50ma) 1mv/ma cl1 output capacitor 1 ldo electrolytic 2.2 10 f esr1 110 cl2 output capacitor 2 ldo ceramic 100 220 nf esr2 0.02 1 w csup1e input capacitor (electrolytic) for emc suppression 22 100 f esr1_csup 110 csup2c input capacitor (ceramic) 100 220 nf esr2_csup 0.02 1 table 20. vcc symbol parameter condition min typ max unit vuvr_off vcc under-voltage threshold off rising edge of vcc 2.55 2.95 v vuvr_on vcc under voltage threshold on falling edge of vcc 2.3 2.7 v vhyst_vcc hysteresis of under-voltage threshold on/off vcc 0.1 0.25 0.4 v table 21. vsup symbol parameter condition min typ max unit vsuvr_off vsup under-voltage threshold off rising edge of vsup 4.8 5.1 5.4 v vsuvr_on vsup under-voltage threshold on falling edge of vsup 3.5 3.8 4.1 v vhyst_vsup hysteresis of vsup under-voltage 1.1 1.5 v www.ams.com revision 0.7 23 - 65 as8515 datasheet - as8515 top die overview 7.16.5 window watchdog timer 7.16.6 lin transceiver dc electrical characteristics. table 22. wwd symbol parameter condition min typ max unit wd_tcl factory setting 1 wwd non-service ti me reset will be generated 0-100 ms wd_tsv wwd service time reset will not be generated 100-200 ms wd_tcl1 factory setting 2 wwd non-service time reset will be generated 0-80 ms wd_tsv1 wwd service time reset will not be generated 80-160 ms wd_tcl2 factory setting 3 wwd non-service time reset will be generated 0-60 ms wd_tsv2 wwd service time reset will not be generated 60-120 ms wd_tcl3 factory setting 4 wwd non-service ti me reset will be generated 0-200 ms wd_tsv3 wwd service time reset will not be generated 200-400 ms wd_tcl4 factory setting 5 wwd non-service ti me reset will be generated 0-160 ms wd_tsv4 wwd service time reset will not be generated 160-320 ms wd_tcl5 factory setting 6 wwd non-service ti me reset will be generated 0-120 ms wd_tsv5 wwd service time reset will not be generated 120-240 ms table 23. driver symbol parameter condition min typ max unit i bus_lim current limitation in dominant state lin = vsup_max 40 120 200 ma lin_v ol output voltage bus (dominant state), i lin = 40ma (short-circuit condition tested at v ol =2.5v) 2v pull-up resistor normal mode (recessive bus level on tx pin) 20 40 60 k i bus_leak_rec driver off; 7.3v < vsup < 18; 8v < v bat < 18, vsup < vbus < 1.08 * vsup (to be tested at vbus = 18v) 20 a table 24. receiver symbol parameter condition min typ max unit i bus_leak_dom input leakage current at receiver driver off; vbus = 0v; vsup = 12v; vcc = 3.3v -1 ma i bus_no_gnd vss = vsup; vsup = 12v; 0v < vbus < 18v, vcc = 3.3v (to be tested at vbus = 18v) -1 1 ma i bus_no_bat vsup = vss; 0v < vbus < 18v, vcc = vss (to be tested at vbus = 18v) 100 a v bus_dom 0.4 vsup v bus_rec 0.6 vsup v bus_cnt v bus_cnt = (v th_dom + v th_rec )/2 1 1. v th_dom : receiver threshold of the recessive to dominant lin bus edge v th_rec : receiver threshold of the dominant to recessive lin bus edge 0.475 0.525 vsup v hys v hys = (v th_dom ? v th_rec ) 1 0.05 0.175 vsup www.ams.com revision 0.7 24 - 65 as8515 datasheet - as8515 top die overview ac electrical characteristics. lin driver, bus load conditions (c bus ; r bus ): 1nf; 1k / 6, 8nf; 660 / 10nf; 500 7.17 timing diagrams figure 15. timing diagram for propagation delays table 25. lin driver symbol parameter condition min typ max unit d1 (worst case 20kbps transmission) v th_rec (max) = 0.744 x v sup ; v th_d om (max) = 0.581 x v sup ; v sup = 6.0v...18v; t bit = 50s; d1 = t bus_rec(min) / (2 x t bit ) 0.396 d2 (worst case 20kbps transmission) v th_rec (min) = 0.422 x v sup ; v th_d om (min) = 0.284 x v sup ; v sup = 6v...18v; t bit = 50s; d2 = t bus_rec(max) / (2 x t bit ) 0.581 d3 (worst case 10.4kbps transmission) v th_rec (max) = 0.778 x v sup ; v th_d om (max) = 0.616 x v sup ; v sup = 6.0v...18v; t bit = 96s; d3 = t bus_rec(min) / (2 x t bit ) 0.417 d4 (worst case 10.4kbps transmission) v th_rec (min) = 0.389 x v sup ; v th_d om (min) = 0.251 x v sup ; v sup = 6v...18v; t bit = 96s; d4 = tb us_rec(max) / (2 x t bit ) 0.59 t dlr vcc = 3.3v; propagation delay bus dominant to rx low 6s t dhr vcc = 3.3v; propagation delay bus dominant to rx high 6s t rs receiver delay symmetry -2 2 s t wake dominant time for wake-up via lin bus 30 150 s t sln transition from standby mode to normal mode (clock frequency is 128khz 25%) 4 clock cycles t nsl transition from normal mode to standby mode (clock frequency is 128khz 25%) 6 clock cycles t rec_deb receiver de-bounce time 0.6 3 s c int internal capacitance of the lin node configured as a slave with a 180pf cap on the lin bus 220 250 pf txd bus rxd 50% 50% 50% 50% 95% 5% 0% 100 % t df_txd t dr_txd t df_rxd t dr_rxd v bus www.ams.com revision 0.7 25 - 65 as8515 datasheet - as8515 top die overview figure 16. timing diagram for duty cycle according to lin 2.1 and j2602 txd bus 100 % v ss 0% t dom(min) t dom(max) t rec(max) t x_dom_max t x_dom_min t x_rec_min t x_rec_max t rec(min) t bit t bit 58.1% 61.6% 28.4% 25.1% 42.2% 38.9% 74.4% 77.8% 58.1% 61.6% 28.4% 25.1% v sup vth_rec(max) vth_dom(max) vth_rec(min) vth_dom(min) t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) lin txd t bit t bit www.ams.com revision 0.7 26 - 65 as8515 datasheet - as8515 top die overview 7.17.1 tx timeout watchdog 7.17.2 temperature limiter 7.18 top die registers the serial interface can be used for communication between as8515 and an external microcontroller. the device is only a slave a nd the microcontroller has to initiate the communication. the device can be configured by writing into the control registers and the d iagnostic information can be read out from the diagnostic registers. pin cst is used as chip select for spi communication. a total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. the registers can be accessed using the 4-wire serial interface. table 28 provides a description of all as8515 top die registers. table 26. tx timeout watchdog symbol parameter conditions min typ max units t lin_wdog timeout period for the dominant state 0.5 1 2 s table 27. temperature limiter symbol parameter conditions min typ max units t sd shut down temperature junction temperature 155 170 185 oc t otset over-temperature warning 142 157 172 oc t ret return temperature 125 140 155 oc table 28. as8515 top die registers address register name default value r/w description configuration and control registers 0x00 reserved 0x01 reserved 0x02 reserved 0x03 device configuration register on por_vcc 0000_1100 r/w d0 reserved d1 voltage attenuator enable bit. 0 disabled, 1 enabled d2 enable/disable over temperature monitor 0 disabled, 1 enabled d3 enable/disable lin transceiver 0 disabled, 1 enabled d4 reserved d5-d7 reserved 0x04 device control register on por_vsup 0000_0001 r/w d0 high-slew / low-slew control 1 high-slew, 0 low-slew d1-d7 reserved 0x05 temporary shutdown register on por_vcc 0000_0000 r/w d0 temporary shutdown control bit 1 enter temporary shutdown d1-d7 reserved 0x06 window watch dog trigger register on por_vcc 0000_0000 w d0 window watchdog trigger bit d1 timeout watchdog trigger bit upon a trigger, the bit will be cleared within 2 internal clock cycles. d2-d7 reserved 0x07 reserved 0x0a reserved 0x0b reserved www.ams.com revision 0.7 27 - 65 as8515 datasheet - as8515 top die overview 0x0c reserved 0x0d reserved 0x0e watchdog timer control register on por_vcc 0000_0000 r/w d0 timer resolution 0 1 second, 1 32 seconds d1-d7 timeout period. if d0=1, then timeout period = d[7:1]*64*0.512 seconds, else timeout period = d[7:1]*0.512 seconds 0x0f reserved diagnostic registers 0x08 diagnostic register-1 on por_vsup 0000_0011 r d7-d0 = dr[7:0], 8-lsb bits of the 24-bit diagnostic register. d0 por-vsup set when vsup < vsuvr_on, cleared after c read d1 under voltage vcc (uvvcc) set when vcc < vuvr_on, cleared after c read d2 over-temperature reset (otemp170) set when temp > t sd , cleared after c read d3 over-temperature warning (otemp160) set when temp > t otset , cleared after c read d4 overvoltag e vsense (ovvsense) set when vsup > vovthh, cleared after c read d5 reserved d6 remote wakeup (rwake) set on remote wakeup event on lin bus, cleared after c read d7 set on failure of window watchdog trigger, cleared after c read 0x09 diagnostic register-2 on por_vsup 0000_0000 r d7-d0 = dr[15:8], next 8-lsb bits of the 24-bit diagnostic register. d0 tx timeout of 1sec (txtimeout) set on tx low > 1sec, cleared after c read d1 tempshut this bit is set on entering temporary shutdown state and cleared after c read. d2 set on failure of timeout watchdog trigger, cleared after c read d3 load dump flag d7-d4 reserved table 28. as8515 top die registers address register name default value r/w description www.ams.com revision 0.7 28 - 65 as8515 datasheet - as8515 bottom die overview 8 as8515 bottom die overview the as8515 bottom die consists of two independent high resolution 16-bit sd analog to digital conversion channels. the measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of current and voltage/temperature. the two measurement channels, namely the current and voltage/temperature measurement channels have identical data path. the input signal is amplified in the programmable gain amplifier (pga) with any of the selected gains of 1, 5, 25, 40 and 100 f acilitating measurement of a wide range of current, voltage and temperature levels. gain settings for different input ranges and any associ ated restrictions are explained in the table 30 . offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. by default the chopper/de-chopper is on in the measurement path. it ma y be disabled by programming the appropriate register. the amplified input signal is converted into a single-bit pulse-density modulated stream by the - modulator. a decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. the decimation ratios of 64, 128 may be selected in the first filter stage. for reducing data rate further, the second stage decimation can be used. an optional fir filter is provided to offer matched low pass filter response typically required in lead acid battery sensor sys tems. 8.1 current measurement channel the voltage across a shunt resistor, connected in series with the battery negative terminal, forms the input signal to the curr ent measurement channel. rshh and rshl are the current measurement input pins. offset in the input signal is nullified with the use of a choppe r and a de- chopper at appropriate stages in the data path. the programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and 100 enables measurement of current ranges from 1a to 1500a on a 100 shunt. the sampled input signal is converted into a single-bit pulse-density modulated stream by the - modulator. a decimator acting as a low-pass filter filters out the quantization noise and generates 16- bit data equivalent to the input current signal. the programmable input sampling rate and the decimation ratio determine the ou tput data rates. the data path can be programmed to provide sub 1hz to 4khz rates in the various modes available. an optional fir filter specifi cally designed for 1khz sample rate is provided to offer matched low pass filter response typically required in lead acid battery sensor syste ms. after enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles. 8.2 voltage/temperature measurement channel the other two parameters of the battery for measurement are voltage and its temperature. the second channel accepts signals fro m four independent sources through a multiplexer as listed below: ?? an attenuator battery voltage obtained through internal resistor divider from top die , (or) ?? a signal from the external temperature sensor, (or) ?? a signal from external reference, (or) ?? a signal from the internal temperature sensor. apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the current mea surement channel. rshh and rshl are the current measurement input pins. the battery voltage which can go up to 18v is attenuated through a resistor divider externally and is applied to the voltage ch annel. for automotive battery measurement, the pga is to be bypassed to con nect battery voltage attenuated by a factor of 21 directly to t he adc input. the latency for the first result from the voltage measurement channel is two conversion cycles. a second option on this measurement channel is to measure temperature. internally generated constant current is pumped through the temperature sensor with positive temperature coefficient, and, a high- precision resistor. the voltages across the sensor and t he resistor form the inputs to the measurement channel one at a time. the difference between the two voltages which is independent of the magnit ude of the current is used to determine the temperature accurately. the voltage across the sensor is applied between the ets and vss pins and, the voltage across the high-precision resistor is applied between et r and vss. external temperature measurement involves the acquis ition of two signals one after the other using the same constant current source. the latency for the first result from the temperature measu rement channel is two conversion cycles. a third option on the measurement channel is to measure the internal temperature. hence, one of the three options for measureme nt of battery voltage, external temperature and, internal temperature may be ca rried out by selection of appropriate inputs through the inter nal multiplexer selection. etr and ets inputs can optionally be used to measure other signal sources like external resistive attenuators for battery volta ges different to 12v nominal. etr and ets are single ended inputs and referenced to avss. voltage drop on internal bond wi re causes ~100 digi ts of offset wit h systematic temperature dependency of another 50 lsb?s over temperature. www.ams.com revision 0.7 29 - 65 as8515 datasheet - as8515 bottom die overview 8.3 digital implementati on of measurement path figure 17. block diagram of digital implementation figure 17 shows the digital implementation of the decimator and filter to process the 1-bit output of the modulator. this block receives a 1-bit pulse density modulated output (mod_in) from the second order sigma delta modulator along with the oversampling frequency clock (mod_clk). the mod_clk directly goes to a clock division block, which generates chopper clock (c hop_clk). the chop_clk can be o ne of 2khz or 4khz selected by register clk_reg in table 49 . the mod_clk can be either 1mhz or 2mhz. the decimation is a two phase process. in the first phase, the r1 down sampling rate can be obtained by selecting either 64 or 128 in registers decreg_r1_i, decreg_r1_v in table 49 . the 16-bit cic1 output is dechopped with respect to chop_clk. the output of dechopper is passed through the cic2 filter with a decimation ratio of 1to 32768 in steps of power of 2. this output is then processed through a fir or moving average (ma) filter. fir filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. ma fil ter is used to provide averaged output and the number of samples for averaging can be any integer value from 1 to 15. 8.4 reference-voltage band gap-reference voltage is used for the adc as a reference and for the generation of the current for external temperature me asurement. 8.5 oscillators a high-speed oscillator (hs) generates the oversampling clock. for internal state machine and interrupt generation, a low-speed oscillator (ls) is also available. 8.6 power-on reset the as8515 has pors, apor and dpor on analog and digital power supplies respectively. on pors of both supplies, initialization sequence happens and the system status is shown in state diagram (see figure 18) . as shown in the state diagram, the system is in reset state until dpor output goes to logic high and subs equently until apor ou tput goes to logic high. once analog power supply is available, the system goes into otp_int state and loads the default values into the con trol and data registers and goes into stop stat e. if analog por, apor goes low at any time, the system goes into reset state. in the stop sta te, the as8515 can be programmed and by giving start command it starts working following the state machine. cic1 64 / 128 clk division block dechopper fir / ma mod_i n mod_clk dataout r1 r1 = first decimation ratio (64 or 128) r2 = second decimation ratio (1 to 32768) mod_clk r1 cic2 r2 fir_ma_sel chp_clk f mod / r1 f chop * 2 f chop * 2 / r2 f chop f mod f chop * 2 / r2 www.ams.com revision 0.7 30 - 65 as8515 datasheet - as8515 bottom die overview 8.7 modes of operation the device operates in four different modes, namely, ?? normal mode 1 (nom1) ?? normal mode 2 (nom2) ?? standby mode 1 (sbm1) ?? standby mode 2 (sbm2) the normal modes are full-power modes with the exception that in normal mode 2, sampling is normally at a programmed lower freq uency and is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measureme nt channel. the standby modes are lower power modes. sampling is normally at a very low frequency interval. in standby mode 2, data samplin g can be carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it gene rates interrupt on the int pin. the device enters into the ?stop? state on power on. this is a state where in the data path is inactive and can be entered into from any of the four modes. the state transition diagram involving the state of stop and the four modes is illustrated in the figure 18 . figure 18. finite state machine model of as8515 bottom die stop otp_int reset norm a_stb por_avdd otp_load stop sbm_on sbm_off s t o p s t a r t s t o p norm or stop analog stablization period wait for 1.5msec 1.5msec & sbm 1.5msec & norm n o r m sbm wait for tt1 timeout t t 1 _ t i m e o u t wait for x number of conversions wait for otp_load completes in 32 cycles of lp_clk !por_avdd sbm !por_dvdd www.ams.com revision 0.7 31 - 65 as8515 datasheet - as8515 bottom die overview figure notes: 1. device soft reset can be written in any of the following states stop, a_stb, sbm_on, sbm_off by writing ?0? into d[7] of the reset _reg (address 0x09). 2. measurement path of soft rese t should be written in any the states, stop, sbm_o ff by writing ?0? into d[6] of the reset _reg (address 0x09). 3. when soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external clock in the application. 8.7.1 normal mode 1 (nom1) on power-on-reset of the device, as8515 goes into stop state. transition to normal mode1 (nom1) occurs when the ?sta rt bit? d0 of mode control register mod_ctl_reg in table 49 is set to ?1? through the serial port spi. data rate of voltage and current channels can be independently programmed and both the channels ge nerate interrupts for every output available from adc. the interrupt signal is generated on the int pin. the width of the interrupt pu lse is eight cycles of l p_clk . the data is stable up to the next interrupt. if the data rate is different for the two channels, the interrupt rate would fol low the higher rate among the two channels. data update can be known by reading the status register. the functionality is explained in the waveform shown in figure 19 . when the device is configured to normal mode1 from any mode the configuration should be through the stop state only. figure 19. normal mode 1 8.7.2 normal mode 2 (nom2) nom2 differs from nom1 in such a way that it allows for a relaxed data rate at a period of t mc by programming the corresponding register as long as the amplitude of current is less than a programmed threshold i thc . however, when, the measured input signal exceeds the programmed threshold, the data rate is changed to the rate of nom1 mode. transition to nom2 occurs when the ?start bit? d0 of mode control register mod_ctl_reg in table 49 is set to 1 and mode control bits to 01 through spi. in this mode the data rate should be programmed with the time of t mc . an interrupt signal is generated on int at the rate of t mc secs with a pulse width of eight cycles of l p_clk . the data is stable up to the next interrupt. the data sample is compared against the programmed threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of nom1 mode. however, as soon as the data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of t mc . the functionality is illustrated in the waveform figure 20 . sampling with f1 int at f1 rate from current channel current channel data register t i start stop t v,t sampling with f2 voltage channel data register interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel i data v,t data t int www.ams.com revision 0.7 32 - 65 as8515 datasheet - as8515 bottom die overview figure 20. normal mode 2 8.7.3 standby mode1 (sbm1) the low-power standby mode can be entered only through the stop st ate. transition to sbm1 mode occurs when the ?start bit? d0 o f mode control register mod_ctl_reg in table 49 is set to ?1? and mode control bits to ?10? through spi. in this mode the date rate is programmable with the time of ta. an interrupt signal is generated on int at the rate of ta seconds, and with a pulse width of eight cycles of l p_clk . the data is stable up to the next interrupt. the functionality is illustrated in figure. during the period of ta, only one data sample is m ade available and, during the rest of the period, the device is maintained in stop state to reduce power consumption. the microcontroller which re ceives the data on the interrupt, is also expected to be processing the data for a short time as shown clearly in the figure 21 to ensure the overall low-power consumption of the data acquisition and processing system. figure 21. standby mode 1 i dd t t mc t mc sampling with f i ths i v,i,t v,i,t v,i,t i > i ths v,i,t v,i,t i < i ths int t int mcu adc t t start sbm1 t a sec. t a sec. t a sec. i dd v, i, t t t v, i, t mcu conv conv conv mcu int channel data register data ? a1 data ? a0 data ? a2 data ? a3 t int www.ams.com revision 0.7 33 - 65 as8515 datasheet - as8515 bottom die overview 8.7.4 standby mode2 (sbm2) standby mode 2 is an extension of the standby mode1 to achieve even a lower power in the data acquisition system by providing i nterrupt to the microcontroller only when the data sample exceeds the set current threshold. the standby mode can be entered only through the s top state. transition to sbm2 mode occurs when the ?start bit? d0 of mode control register mod_ctl_reg in table 49 is set to ?1? and mode control bits d7,d6 to ?1,1? through spi. in this mode the date rate is pr ogrammable with the time of ta in the ta control registers b, c. the data sample is made available and an interrupt signal is generated on int pin only when the input signal exceeds the threshold set in curre nt threshold registers d,e. it should be noted here that the data is stable for ta seconds. the functionality is illustrated in figure 22 . figure 22. standby mode 2 8.8 initialization se quence at power on figure 23. bottom die device initialization sequence at power on device initialization starts if the dvdd and avdd supplies are switched on and dvdd > v porhid . the duration period of initialization is 500 sec and during this period, int pin toggles at the rate of internal low power oscillator. toggling on int during the period of init ialization should be ignored in the system. device configuration and activation should be carried out only after the initialization period. on adc start, device enters into analog stabilization state and takes 1.5msec for oscillator and reference to settle. after thi s 1.5msec period, the first interrupt will occur after a time period of t adc . adc t t conv start sbm2 t a sec. t a sec. t a sec. i dd i t conv t conv i mcu |i| > i threshold int channel data register data ? a1 data ? a0 data ? a2 data ? a3 t int configure device start adc dvdd/avdd por_n int chop_clk channel data register 0x0000 data1 data2 d1 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 500s 1.5ms t data_status_rd t data_valid t data_invalid v porhid /v porhia t adc www.ams.com revision 0.7 34 - 65 as8515 datasheet - as8515 bottom die overview t data _ status _ rd is the time period during which the micro-controller should complete reading of data and status from the device. if reading is carried out beyond this time period, then, adc performance will degrade for next sample generation. status register gets cleare d automatically only when micro-controller reads this register. data in the channel registers is changed after t data _ valid duration. ensure that data channel registers and status registers are not read during the t data _ invalid duration. example: configuration registers are set as follows: clk_reg = 8?b0010_0000 dec_reg_r1_i = 0100_0101 dec_reg_r2_i = 1100_0101 fir_ctl_reg_i = 0000_0100 adc is configured to a data rate of 1khz, chop_clk to 2khz, and modulator clock to 1mhz, decimation ratio of cic1 = 64, and dec imation ratio of cic2 = 4. with these settings the various time periods as shown in the figure 23 are as follows: t data _ status _ rd = 100 sec (t data _ status _ rd = (1/mod_clk) * r1 * [((mod_clk/(2*chop_clk))*(1/r1)) - 2.5) t data _ invalid = 8 sec t adc = 1msec t data _ valid = t adc - t data _ invalid = 1msec - 8 sec chop_clk and por_n are internal signals of the device. table 29 provides valid combinations of modulator clock, chopper clock and decimation r1 and the corresponding values of t data _ status _ rd and t adc . 8.8.1 soft-reset of device using bit d[7] of reset register 0x09 it is possible to soft-reset the device by writing ?0? into d[7] bit of reset register at 0x09. on applying soft-reset, the dev ice enters into initialization state and d[6] bit changes back to ?1?. the duration period of initialization is 500 sec, and, during this period, int pin toggles at the rate of internal low power oscillator. toggling on int during the period of initialization should be ignored in the system. dev ice configuration and activation should be carried out only after the initialization period. see figure 24 for the timing details of the sequence of device initialization on soft-reset. table 29. valid combinations of modulator clock, chopper clock and decimation ratio r1 modulator clock chopper frequency chop_clk decimation ratio r1 t data _ status _ rd t adc r2/(2*chop_clk) for r2=4 1.024mhz 2khz 64 1usec * 64 * [4 - 2.5] = 96usec 1msec 2.048mhz 2khz 64 0.5usec * 64 * [8 - 2.5] = 176usec 1msec 2.048mhz 2khz 128 0.5usec * 128 * [4 - 2.5] = 96usec 1msec 2.048mhz 4khz 64 0.5usec * 64 * [4 - 2.5] = 48usec 0.5msec www.ams.com revision 0.7 35 - 65 as8515 datasheet - as8515 bottom die overview figure 24. bottom die device initialization sequence at soft-reset 8.8.2 soft-reset of the measurement path using bit d[7] of reset register 0x09 measurement path also can be reset by using d[6] bit of reset register at 0x09. on applying soft-reset only signal measurement path registers will be reset. for applying this reset, device should be in stop state. if the device is working with external clock, at the ti me of soft-reset the clock needs to be disabled. 8.8.3 reconfiguring gain setting of pga only pga gain settings can be changed dynamically while adc conversions are in progress. when pga gain settings are changed, th e first sample from the adc is invalid. ignore the first interrupt after the gain re-configuration. valid data starts from the second i nterrupt onwards. figure 25. bottom die - re-configuration of gain setting of pga 8.8.4 configuring the de vice during normal mode following registers can be programmed dynamically when the device is in operational mode (normal mode). ?? ach_ctl_reg address is 0x17 for channel selection on the voltage measurement path ?? pga_ctl_reg address is 0x13 for gain setting ?? pd_ctl_reg2 address is 0x15 for pga bypass ?? isc_ctl_reg address is 0x18 for current source programmability during the operation (normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned registers, then it is required to stop the device by writing in to mod_ctl_reg ?stop? bit and configure the device as per the re quirements and start the device. data-n data-n+1 d4 d1 d2 d3 d4 d1 t data_status_rd t data_valid t data_invalid re-configure device start adc int chop_clk channel data register 0x0000 data1 data2 d1 d2 d 3 d4 d1 d2 d3 d4 d1 d2 d3 d4 500s 1.5ms t data_status_rd t data_valid t data_invalid soft reset using d7 data-n data-n+1 d4 d1 d2 d3 d4 t data_status_rd t data_valid t data_invalid int chop_clk channel data register data1 data2 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 t data_status_rd t data_valid t data_invalid d1 t data_status_rd gain re-configuration can be carried out in this slot, skip next interrupt and channel data. read channel data in this slot valid data www.ams.com revision 0.7 36 - 65 as8515 datasheet - as8515 bottom die overview 8.8.5 standby mode - power consumption in standby mode 1 there is a timer based accurate measurement every ta seconds. the device itself stays in idle-mode as long as it does not get a different command from the spi interface. internal oscillator frequency is typically foscint=262 khz to reduce power cons umption as long as the timer runs. after every time out of ta seconds, it performs accurate measurement of current, voltage/ temperature. data rea dy is signaled to microcontroller through an interrupt signal on int and goes into stop state. in the sbm the following equations hold: ?? t sbm1 = ta= 10s (default value is 10secs); the power consumption is valid for this setting. this is the period of the repetition rate in sbm 1 and sbm2. ?? t sett 2ms (depending on external capacitors). this is the time required by the analog part to settle when the new measuring period i s started. any measurements performed during t sett produce invalid results. ?? t1 = 3ms (by default setting, every third measurement is sent to microcontroller in the sbm mode 1) is the time needed to perfo rm the first measurement. ?? t meas =t sett +t1 is the total active time needed to get a valid result. ?? dr sbm = t meas /t sbm 5ms/10s. this is the ratio of repetition time versus the active time (device in nom mode). power consumption = (dr sbm *nom mode power consumption) + ((10s-5ms)/10s)*stop mode power consumption) 8.9 bottom die bl ock specifications this section provides specification of design related key parameters. 8.9.1 current measurement ranges (across 100 (5%) shunt resistor) note: the data rate at the output can be calculated according to the formula: fsout=2*fchop /r2 (r2 is down sampling ratio taki ng values 1, 2, 4 up to 32768 as powers of 2) table 30. current measurement ranges symbol parameter i max [a] v sh [mv] pga gain nominal data rate (f out ) v inadc 1 [mv] 1. v inadc = v sh * gain, gain deviations to be considered according to table 32 and table 33 . psr 2 [db] 2. avdd, dvdd of 3.3v with 5% variation. i70 input current range of 70a in nom 77 8.1 100 @ 1 khz 890 60 i200 input current range of 200a in nom 235 24.7 40 @ 1 khz 1088 60 i400 input current range of 400a in nom 400 42 25 @ 1 khz 1137 60 i1500 input current range of 1500a in nom +2076/-1523 +218/-160 5 @ 1 khz 1204 60 table 31. valid combinations of the chopper clock, oversampling clock and decimation ratios over sampling frequency chopper frequency decimation ratio 1.024mhz 2khz 64 2.048mhz 2khz 64 2.048mhz 2khz 128 2.048mhz 4khz 64 www.ams.com revision 0.7 37 - 65 as8515 datasheet - as8515 bottom die overview differential input amplif ier for current channel. notes: 1. leakage test accuracy is limited by tester resource accuracy and tester hardware. 2. for gain 100 pga input common mode is 0v and the minimum supply is 3.15v. 3. the measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro- grammed independently. 4. this parameter is not measured directly in production. it is measured indirectly via gain measurements of the whole path. i t is guaran- teed by design. 5. pole frequency of input amplifier changes with gain. the number is valid for the gain at g1, while the bandwidth will be hi gher for other ranges. this parameter is not measured in production. 6. based on device evaluation. not tested. 7. these offsets are cancelled if chopping enabled (default). 8. noise density calculated by taking system bandwidth as 150hz. 9. refer to measurement ranges shown in table 30 . 10. no impact on the measurement path. if the chopping is enabled, both the offset and offset drift will be eliminated. 11. for negative input voltages up to -160mv below ground, inpu t leakage is typically -20na @ 65oc due to forward conductance of protection diode. table 32. differential input amplifier for current channel symbol parameter conditions min typ max units v in _amp input voltage range rshh and rshl -160 +160 mv i in _amp input current 1, 11 rshh and rshl@ +160mv input voltage at 125oc with pga -50 2 50 na icm absolute input voltage range 2 -160 +300 mv g = g1 gain1 3, 4, 9 i10 100 g = g2 gain2 3, 4, 9 i200 40 g = g3 gain3 3, 4, 9 i400 25 g = g4 gain4 3, 4, 9 i1500 5 e gain deviation i = 1, 2, 3, 4 0.9 * gi 1.1 * gi f p _amp pole frequency 4, 5 15 khz t1 gain drift with temperature 6 -20oc to +65oc gain 5, 25, referenced to room temperature 0.5 % v osdrift offset drift with temperature 7, 10 350 v v os input referred offset 7, 10 after trim at -20deg 350 v v os_ch chopping enabled 0 lsb v ndin noise density 4, 8 25 nv/ hz thd total harmonic distortion for 150 hz input signal 70 db www.ams.com revision 0.7 38 - 65 as8515 datasheet - as8515 bottom die overview differential input amplifier for voltage channel. notes: 1. input for the voltage channel can be as high as 1220mv, in this high input case pga will be bypassed. 2. leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to con densing moisture. 3. for gain 100 pga input common mode is 0v and the minimum supply is 3.15v. 4. the measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro- grammed independently. 5. this parameter is not measured directly in production. it is measured indirectly via gain measurements of the whole path. i t is guaran- teed by design. 6. pole frequency of input amplifier changes with changing the gain. the number is valid for the gain at g1, while the bandwid th will be higher for other ranges. this parameter is not measured in production. 7. noise density calculated by taking system bandwidth as 150hz. 8. based on device evaluation. not tested. 9. no impact on the measurement path. if the chopping is enabled, both the offset and offset drift will be eliminated. 10. for negative input voltages up to -160mv below ground, inpu t leakage is typically -20na @ 65oc due to forward conductance of protection diode. table 33. differential input amplifier for voltage channel symbol parameter conditions min typ max units v in_ amp input voltage range 1, 10 -160 +160 mv i in_res input resistance 2, 10 vbat_in, etr, ets @ +160mv input voltage at 125oc with pga 12.5 k icm absolute input voltage range 3 -160 +300 mv g = g1 gain1 4, 5 100 g = g2 gain2 4, 5 40 g = g3 gain3 4, 5 25 g = g4 gain4 4, 5 5 e gain deviation i = 1, 2, 3, 4 0.9 * gi 1.1 * gi f p _amp pole frequency 5, 6 15 khz v ndin noise density 5, 7 25 nv/ hz thd total harmonic distortion for 150hz input signal 70 db t 1 gain drift with temperature 8 -20oc to +65oc gain 5, 25, referenced to room temperature 0.5 % v os input referred offset 9 after trim at -20oc 350 v v os_ch chopping enabled 0 lsb v osdrift offset drift with temperature 9 350 v www.ams.com revision 0.7 39 - 65 as8515 datasheet - as8515 bottom die overview sigma delta analog to digital converter. notes: 1. production test at 800mv. maximum v in can be 1.22v with vref=1.225v. 2. programmable. it is defined with respect to the first decimator in the ? adc. 3. programmable: internal clock is 1024/2048 khz; external clock max is 8192 khz. 4. dependent on fovs, r1 and r2. the bandwidth is calculated according to the formula: bw=fovs/(2*r1*r2); the sampling frequency at the output of the a/d converter is 2*bw. 5. defined at maximum input signal, bw=500 hz (1hz to 500 hz), fovs=1024 khz, r1=64, fchop=2 khz and r2=2. 6. reference voltage might be forced from external. bandgap reference voltage. notes: 1. accuracy at 65oc. no dc current is allowed from this pin. 2. specification does not include solder shift and life time drift. 3. please refer figure 26 for typical life time drift based on system level measurements. 4. this is a design parameter and not production tested. table 34. sigma delta analog to digital converter symbol parameter conditions min typ max units v ref reference voltage 6 1.225 v v inadc input range 1 at v ref = 1.22v 01.22v r1 oversampling ratio/decimation ratio 2 64 128 128 f ovs oversampling frequency 3 1024/ 2048 khz res number of bits 16 bits bw bandwidth 4 1 500 hz s/n signal to noise ratio 5 90 db table 35. bandgap reference voltage symbol parameter conditions min typ max units v reftrim reference voltage after trim 1, 2, 3 trim at 65oc 1.225 v v refacc reference voltage initial accuracy 1, 2, 3 at 65oc (0 hour data) 3.5 mv v ref drift reference voltage temperature drift temperature range -20oc to 65oc 0.4 % temperature range -40oc to 125oc +0.4/ -0.6 % psrr ref psr @ dc 80 db sut avdd start up time with supply ramp 4 5ms sut pd start up time from power down 4 1ms r ndvref output resistance of band gap 500 1000 v ndvref bandgap reference thermal noise density 4 300 nv/ hz cl vref output capacitor (ceramic) 100 nf esr vref 0.02 1 www.ams.com revision 0.7 40 - 65 as8515 datasheet - as8515 bottom die overview figure 26. typical system-level v ref drift 1.2230 1.2235 1.2240 1.2245 1.2250 1.2255 1.2260 1.2265 0 50 100 150 200 250 300 dut1 dut2 dut3 dut4 0.10% -0.10% ref-voltage [v ref ] system level operating time in no rmal mode at 115oc ambient [h] as8515 www.ams.com revision 0.7 41 - 65 as8515 datasheet - as8515 bottom die overview internal (programmable) current source for external temperature measurement. notes: 1. current value can be programmed through stop mode in steps of 8 a from 0 to 256 a with a process error of 30%. 2. temperature coefficient is not important since external temperature measurement is a 2 step measurement. the value specifie d is guaranteed by design and will not be tested in production. 3. maximum voltage on pin etr (reference) can be calculated by given formula, where g is the gain of pga (g=100). 4. maximum voltage on pin etr, if pga is bypassed. 5. maximum voltage on pin ets, if pga is bypassed. cmref circuit (vcm). internal avdd power-on reset. table 36. external temperature measurement symbol parameter conditions min typ max units i curon 5-bit current source enabled 1 5-bit programmable current source 0 270 320 a i curoff 5-bit current source disabled limited by leakage 10 na t k _ cs temperature coefficient of current source 2 1000 ppm / ok v maxetr voltage on pin etr 3 1000/g mv v maxetrmod max voltage on pin etr when pga is bypassed 4 1.22 v v maxets voltage on pin ets for resistor sensor 3 1000/g v v maxetsmod max. voltage on pin ets when pga is bypassed 5 1.22 v table 37. cmref circuit symbol parameter min typ max units v vcm output voltage 1.6 1.7 1.8 v c l load capacitance 100 nf table 38. internal avdd power-on reset symbol parameter min typ max units v porhia power on reset threshold 2.2 2.4 2.6 v t pora por time - the duration from power on till the time, internal power on reset signal goes high 1 1. por pulse is always longer than t pora whatever the slope of the supply. 1s i pora current consumption in por block 2 2. i pora can not be switched off. 1.5 a www.ams.com revision 0.7 42 - 65 as8515 datasheet - as8515 bottom die overview internal dvdd power-on reset. low speed oscillator. high speed oscillator. notes: 1. accuracy after trimming. external clock. table 39. internal dvdd power-on reset symbol parameter min typ max units v porhid power on reset threshold 2.2 2.4 2.7 v v hyst hysteresis 1 1. v porlo = v porhi - v hyst where v porlo is the lower threshold of por. 0.2 0.25 0.4 v t pord por time - the duration from power on till the time, internal power on reset signal goes high 2 2. v porlo = v porhi - v hyst where v porlo is the lower threshold of por. 1s i pord current 3 3. i pord can not be switched off. 1.5 a table 40. low speed oscillator symbol parameter min typ max units f ls frequency 262.144 khz f ls _ acc accuracy 7 % i ls supply current 5 a table 41. high speed oscillator symbol parameter min typ max units f hs frequency 4.096 mhz f hsacc accuracy 1 4 % i hs supply current 300 a table 42. external clock symbol parameter conditions min typ max units f clkext clock frequency 2048/ 4096/ 8192 khz div clkext clock division factor to be programmed in register 08 clk_reg through the serial bus spi. 2/4/8 dc clkext duty cycle of external clock 40 60 % www.ams.com revision 0.7 43 - 65 as8515 datasheet - as8515 bottom die overview internal temperature sensor. 8.9.2 system specifications system measurement error budget for voltage and current channel. temperature range: -20oc to +65oc; output data rate is 1khz, v cc = 3.3v, chopping enabled. notes: 1. these specifications are defined by taking one channel as reference and measured on the other channel. 2. guaranteed by design. 3. system measurement error due to noise, individual block parameter drifts and non linearity. based on evaluation, not tested . 4. system error due to offset is neglected because of chopper architecture. table 43. internal temperature sensor symbol parameter conditions min typ max units t intrng temperature sensor range -40 125 oc tin temperature measurement accuracy 3 oc t intslp temperature sensor slope guaranteed by design; at pga gain 5 which is the recommended gain for internal temperature measurement. 27 digits/c t int 65 g 5 temperature sensor output at gain 5 40660 41807 43012 digits table 44. system specifications symbol parameter min typ max units i s channel to channel isolation 1 -90 db at difference in channel to channel attenuation @600hz 1, 2 3db ph difference in phase shift between the two channels @600hz 1, 2 5deg table 45. system measurement error budget for gains 5 and 25 symbol parameter conditions min typ max units err system measurement error 3, 4 0.6 1 % measurement error due to pga gain drift from device evaluation 0.5 % measurement error due to v ref drift 0.4 % measurement error due to non-linearity of pg tested by distortion measurements 0.025 % www.ams.com revision 0.7 44 - 65 as8515 datasheet - 4-wire spi interface 9 4-wire spi interface the spi interface can also be used as interface between the as8515 and an external micro-controller to configure the device and access the status information. micro-controller begins communication with the spi configured as a slave. the spi protocol is very simple a nd the length of each frame is an integer multiple of byte except when a transmission is started. basically each frame has 1 command bits, 5 add ress/ configuration bits, 1 or more data bytes. spi clock polarity settings depend on the value of the sclk on the cs falling edge. t his setting is done on each start of the spi transaction. during the transaction spi clock polarity will be fixed to the settings done. on the cs f alling edge the values on sclk signal decide setting of the active spi clock edge for data transfer (see table 46) . 9.1 spi timing parameters table 46. cs and sclk cs 1 1. pin cst is used to program top device and pin csb is used to program bottom device. sclk description fall low serial data transferred on rising edge of spi clock. sampled at falling edge of spi clock. fall high serial data transferred on falling edge of spi clock. sampled at rising edge of spi clock. any any serial data transfer edge is unchanged. table 47. 4-wire serial port interface symbol parameter conditions min typ max units general br spi bit rate 250 kbps t sclkh clock high time 2 s t sclkl clock low time 2 s write timing t dis data in setup time 20 ns t dih data in hold time 10 ns t csh cs hold time 20 ns read timing t dod data out delay 80 ns t dohz data out to high impedance delay time for the spi to release the sdo bus 80 ns timing parameters when entering 4-wire spi mode (for determination of clk polarity) t cps clock setup time (clk polarity) setup time of sclk with respect to cs falling edge 20 ns t cphd clock hold time (clk polarity) hold time of sclk with respect to cs falling edge 20 ns www.ams.com revision 0.7 45 - 65 as8515 datasheet - 4-wire spi interface 9.1.1 spi frame a frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an int eger number of bytes. command is coded on the 1 first bit, while address is given on lsb 5 bits (see table 48) . if the command is read or write, one or more bytes follow. wh en the micro-controller sends more bytes (keeping cs low and sclk toggling), the spi interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. 9.1.2 write command for write command c0 = 0. after the command code c0 and two reserved bits, the address of register to be written has to be provided from the msb to the l sb. then one or more data bytes can be transferred, always from the msb to the lsb. for each data byte following the first one, used address is the incremented value of the previously written address. each bit of the frame has to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. these edges are selected as per clock polarity settings. in the following figures two examples of write command (without and with address self-increment. figure 27. protocol for serial data write with length = 1 table 48. command bits command bits register address or tr ansmission configuration c0 reserved reserved a4 a3 a2 a1 a0 c0 command www.ams.com revision 0.7 46 - 65 as8515 datasheet - 4-wire spi interface figure 28. protocol for serial data write with length = 4 9.1.3 read command for read command c0=1. after the command code c0 and two reserved bits, the address of register to be read has to be provided from the msb to the lsb. then one or more data bytes can be transferred from the spi slave to the master , always from the msb to the lsb. to transfer more bytes fro m consecutive addresses, spi master has to keep active the spi cs signal and the spi clock as long as it desires to read data from the slave. each bit of the command and address sections of the frame have to be driven by the spi master on the spi clock transfer edge and the spi slave on the next spi clock edge samples it. each bit of the data section of the frame has to be driven by the spi slave on the spi clock transfe r edge and the spi master on the next spi clock edge samples it. these edges are selected as per clock polarity settings. in the following figures , two examples of read command (without and with address self-increment) have been shown. figure 29. protocol for serial data read with length = 1 cs sclk sdi sdo 0 re s1 a 1 a 4 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 data d7-d0 is moved to address a4-a0 here data d7-d0 is moved to address a4-a0 +1 here data d7-d0 is moved to address a4-a0 +2 here data d7-d0 is moved to address a4-a0 +3 here data d7-d0 is moved to address a4-a0 +4 here a 0 re s0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 cs sclk sdi sdo 1 res1 res0 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 at address a4..a0 is read here transfer edge sampling edge www.ams.com revision 0.7 47 - 65 as8515 datasheet - 4-wire spi interface figure 30. protocol for serial data read with length = 4 9.1.4 timing in the following figures timing waveforms and parameters are exposed. figure 31. timing for writing cs sclk sdi sdo 1 re s1 re s0 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 data d7-d0 at address a4-a0 is read here data d7-d0 at address a4-a0 +1 is read here data d7-d0 at address a4-a0 +2 is read here data d7-d0 at address a4-a0 +3 is read here data d7-d0 at address a4-a0 +4 is read here cs sdi sdo sclk ... ... ... t cps t cphd t dis t dih clk polarity datai datai datai ... t csh t sclkh t sclkl www.ams.com revision 0.7 48 - 65 as8515 datasheet - 4-wire spi interface figure 32. timing for reading 9.2 bottom die registers this section describes the control registers used in as8515 bottom die . registers can be broadly classified into the following categories. ?? data access registers ?? status registers ?? digital signal path control registers ?? digital control registers ?? analog control registers table 49. control registers addr in hex register name por value r/w 8-bit control / status data data access registers 00 dreg_i1 (adc data register for current) 0000_0000 r d[7:0] denotes the current adc msb byte (adc_i[15:8]) 01 dreg_i2 (adc data register for current) 0000_0000 r d[7:0] denotes the current adc lsb byte (adc_i[7:0]) 02 dreg_v1 (adc data register for voltage) 0000_0000 r d[7:0] denotes the voltage adc msb byte (adc_v[15:8]) 03 dreg_v2 (adc data register for voltage) 0000_0000 r d[7:0] denotes the voltage adc lsb byte (adc_v[7:0]) cs sclk sdi sdo t dohz t dod datai datai datao (d7 ) datao (d0) t sclkh t sclkl www.ams.com revision 0.7 49 - 65 as8515 datasheet - 4-wire spi interface status registers 04 status_reg 0000_0000 r d[7] nom1/nom2 data ready d[6] nom2 threshold crossover d[5] sbm1 data ready d[4] sbm2 threshold crossover d[3] apor status d[2] data from current channel updated d[1] data from voltage channel updated d[0] reserved table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 50 - 65 as8515 datasheet - 4-wire spi interface digital signal path control registers for current channel 05 dec_reg_r1_i 0100_ 0101 r/w d[7] this bit selects decimation rate is used for current channel. default is 0 (down sampling rate is 64) 0 down sampling rate is 64 1 down sampling rate is 128 d[6:5] these two bits select division ratio of oversampling frequency clock mod_clk to be used as chopper clock, chop_clk. default is ?10? (divide by 512) 00 chopper clock always high 01 divide by 256 10 divide by 512 11 divide by 1024 d[4:1] these four bits select the decimation ratio of second cic stage. default is ?0010? (equal to 4) 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 d[0] cic1 saturation interrupt mask control. default is 1 0unmask 1mask table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 51 - 65 as8515 datasheet - 4-wire spi interface 06 dec_reg_r2_i 1100_0101 r/w d[7] i-channel enable, default 1=enable d[6] v-channel enable, default 1=enable d[5] interrupt polarity 0 active high 1 active low d[4] . interrupt mask control for current channel data ready interrupt on int pin (default is 0) 0unmasked 1masked d[3:2] these two bits select the source of output 16-bit data in normal mode from current channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic1 output d[1:0] these two bits select the source of output 16-bit data in sbm mode from current channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic1 output table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 52 - 65 as8515 datasheet - 4-wire spi interface 07 fir ctl_reg_i 0000_0100 r/w d[7] this bit selects fir / ma filter in current channel. default is 0 (fir) 0fir 1ma filter d[6:3] these bits select the number of data samples for averaging in ma filter in current channel. default is 0000 (bypass) 0000 bypass 0001 1 0011 3 0111 7 1111 15 d[2:1] these two bits select the measurement path architecture in both current and voltage channels. default is 10 (dechopper after cic) 00 demodulator after cic1 01 demodulator before cic1 10 dechopper after cic1 (preferred and suggested) 11 demodulator before cic1 with settled sample d[0] reserved. default 0. do not change table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 53 - 65 as8515 datasheet - 4-wire spi interface digital control registers 08 clk_reg (clock control register) 0010_0000 r/w d[7:6] oversampling frequency clock selection. default is 00 (high speed (hs) internal clock) 00 internal hs clock with no clock output 01 internal hs clock with clock output 10 external clock d[5:4] these two bits select the division ratio for hs clock/ external clock. default is 10 (division by 4) 00 no division 01 divide by 2 10 divide by 4 11 divide by 8 d[3:2] these two bits select the division ratio of hs clock, by which it should be divided before providing it on clk pin. default is 00 (no division) 00 no division 01 divide by 2 10 divide by 4 11 divide by 8 d[1] this bit selects the division ratio of ls clock 0 ls _clk undivided (low speed clock) 1 ls _clk divide by 2 d[0] reserved 09 reset_reg (reset control register) 1100_0000 r/w d[7] entire device can be soft reset by writing ?0? into this register bit. this bit will take a default 1 value on coming out of reset d[6] measurement path can be soft reset by writing ?0? into this register bit. this bit will take a default 1 value after measurement path is reset. d[5:0] reserved table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 54 - 65 as8515 datasheet - 4-wire spi interface 0a mod_ctl_reg (mode control registers) 0000_0000 r/w d[7:6] these two bits select the operating mode of the device. default is 00 (normal mode 1) 00 normal mode 1 01 normal mode 2 10 standby mode 1 11 standby mode 2 d[5:3] these three bits select the number of cycles to be ignored before comparison with the set threshold in standy mode. default is 000 (3 cycles of data) 000 3 cycles of data 001 4 cycles of data 010 5 cycles of data 011 6cycles of data 100 7 cycles of data 101 8 cycles of data 110 9 cycles of data 111 10 cycles of data d[2] this bit controls the chop_clk availability on chop_clk pin. default is 0 0 disabled 1 enabled d[1] enabling the men pin to indicate transition from standby to normal mode. 0 disabled 1 enabled d[0] this bit is used to take the device from stop state to any of the modes based on d[7:6] selection of this register. 0 retain in stop state 1 enables transition to normal or standby modes. 0b mod_ta_reg1 (ta control register) 1000_0000 d[7] unit of ta in sbm1/sbm2. default is 1 0 unit is in milliseconds 1 unit is in seconds d[6:0] msb value of ta 0c mod_ta_reg2 (ta control register) 0000_0000 r/w d[7:0] unit of ta in sbm1/sbm2 lsb value of ta 0d mod_i th _reg1 (current threshold register) 0000_0000 r/w d[7:0] msb bits of 16 bits sbm2 threshold register 0e mod_i th _reg2 (current threshold register) 0000_0000 r/w d[7:0] lsb bits of 16 bits sbm2 threshold register table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 55 - 65 as8515 datasheet - 4-wire spi interface 0f mod_t mc _reg1 (t mc control registers) 0000_0000 r/w d[7:0] msb value of number of data samples to be dropped from adc before sending interrupt in nom2 10 mod_t mc _reg2 (t mc control register) 0000_0000 r/w d[7:0] lsb value of number of data samples to be dropped from adc before sending interrupt in nom2 11 nom_i th _reg1 0000_0000 r/w d[7:0] eight msb bits of nom2 current threshold register 12 nom_i th _reg2 0000_0000 r/w d[7:0] eight lsb bits of nom2 current threshold register analog control registers 13 pga_ctl_reg (pga control registers) 0101_0000 r/w d[7:6] setting of gain g of current channel pga. default is 01 (g = 25) 00 5 01 25 10 40 11 100 d[5:4] setting of gain g in voltage channel. default is 01 (g = 25) 00 5 01 25 10 40 11 100 d[3:0] reserved 14 pd_ctl_reg_1 (power down control register) 1100_1111 r/w d[7] 0 disable chopper clock to current channel 1 enable chopper clock to current channel d[6] 0 disable chopper clock to voltage channel 1 enable chopper clock to voltage channel d[5] reserved d[4] reserved d[3] 0 disable current channel pga 1 enable current channel pga d[2] 0 disable current channel ? modulator 1 enable current channel ? modulator d[1] 0 disable voltage channel pga 1 enable voltage channel pga d[0] 0 disable voltage channel ? modulator 1 enable voltage channel ? modulator table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 56 - 65 as8515 datasheet - 4-wire spi interface 15 pd_ctl_reg_2 (power down control register) 1111_0011 r/w d[7] 0 disable cic1 of both channels 1 enable cic1 of both channels d[6] 0 disable cic2 of both channels 1 enable cic2 of both channels d[5] 0 disable dechopper in both channels 1 enable dechopper in both channels d[4] 0 disable fir in both channels 1 enable fir in both channels d[3] 0 do not bypass pga in current channel default 0 1 bypass pga in current channel d[2] 0 do not bypass pga in voltage channel default 0 1 bypass pga in voltage channel note: for automotive battery measurement, ensure that the pga is bypassed to connect battery voltage (attenuated by factor of 21) directly to the adc input. d[1] 0 disable current channel chopper 1 enable current channel chopper d[0] 0 disable voltage channel chopper 1 enable voltage channel chopper 16 pd_ctl_reg_3 (power down control register) 1111_1000 d[7] 0 disable common mode reference 1 enable common mode reference d[6] 0 disable internal current source 1 enable internal current source d[5] 0 disable internal temperature sensor 1 enable internal temperature sensor d[4] reserved. (default 1) do not change d[3] reserved. (default 1) do not change d[2] 0 data output in binary numbering system 1 data output in 2?s complement numbering system d[1] reserved. (default 0) do not change d[0] reserved table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 57 - 65 as8515 datasheet - 4-wire spi interface 17 ach_ctl_reg (analog channel selection register) 0000_0000 r/w d[7:6] these bits specify the selection of voltage/temperature in voltage channel default is 00 (voltage channel) 00 voltage channel 01 external temperature channel etr 10 external temperature channel ets 11 internal temperature channel d[5] reserved. (default 0) do not change d[4] internal current source switch enable. default is 0 note: d4 bit is used for enabling current source to the channel selected by bits d[7,6] of this register. 0 disabled 1 enabled d[3] enable/disable internal current source to rshh pin of current channel 0 disabled 1 enabled d[2] enable/disable current source switch to rshl pin of current channel 0 disabled 1 enabled d[1:0] reserved 18 isc_ctl_reg (current source setting register) 0000_0000 r/w d[7:3] these three bits specify the selection of magnitude of current from the internal current source. default is 00000 (0a). 00000 0a 00001 8.5a 00010 17a 00100 34.5a 01000 68a 10000 135a 11111 270a d[2:0] reserved 19 otp_en_reg 0000_0000 r/w d[7] 1 reserved (default = 1) do not change d[6:0] reserved 44 status_reg_2 0000_0000 r d[7] status indicating data saturation in current channel d[6] status indicating data saturation in voltage channel d[5:0] reserved table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 58 - 65 as8515 datasheet - 4-wire spi interface digital signal path control registers for voltage channel 45 dec_reg_r1_v 0100_ 0101 r/w d[7] selection of decimation ratio for voltage/temperature channel. default is 0 (down sampling rate is 64) 0 down sampling rate is 64 1 down sampling rate is 128 d[6:5] division of oversampling clock, which is used as chopper clock. default is 10 (divide by 512) 00 chopper clock always high 01 divide by 256 10 divide by 512 11 divide by 1024 d[4:1] decimation ratio of cic2. default is 0010 (4) 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 d[0] cic1 saturation interrupt mask control. default is 1 0unmasked 1masked table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 59 - 65 as8515 datasheet - 4-wire spi interface note: all the registers from address 0x19 to 0x2c are read-only. 46 dec_reg_r2_v 0000_0100 r/w d[7:5] reserved d[4] interrupt mask control for voltage channel data ready interrupt on int pin (default is 0) 0unmasked 1masked d[3:2] these two bits select the source of output 16-bit data in normal mode from voltage channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic output d[1:0] reserved 47 fir ctl_reg_v 0000_0000 r/w d[7] this bit selects fir / ma filter in voltage channel. default is 0 (fir) 0fir 1ma filter d[6:3] these bits select the number of data samples for averaging in ma filter in voltage channel. default is 0000 (bypass) 0000 bypass 0001 1 0011 3 0111 7 1111 15 d[2:0] reserved table 49. control registers addr in hex register name por value r/w 8-bit control / status data www.ams.com revision 0.7 60 - 65 as8515 datasheet - application information 10 application information figure 33. application diagram note: keep the differential input signal lines short, symmetric, and as close as possible. use of pcb shielding layers is recommended , but consider eddy currents for fast changes in shunt current and related parasitic signal / ground shift generation. note: vsense_in, vsense_gnd, men, and cho p_clk should be left unconnected. 100nf 100nf 12v battery +- 100ohm csb int cst tx rx reset rshh rshl vref vcm avdd avss etr ets vsense_in vsense_gnd vss vsup lin en vsense vcc as8515 sdi men chop_clk sdo dvdd dvss sclk clk 3.3v 3.3v 2.2f 100nf vbat diode 22f 200nf sup diode c 10k optional 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c lin 100nf load www.ams.com revision 0.7 61 - 65 as8515 datasheet - package drawings and markings 11 package drawin gs and markings the devices are available in a 32-pin mlf (5x5 mm) package. figure 34. package drawings and dimensions as8515 yywwvzz @ www.ams.com revision 0.7 62 - 65 as8515 datasheet - package drawings and markings notes: 1. dimensions and tolerancing conform to asme y14.5m -1994 . 2. all dimensions are in millimeters. angles are in degrees. 3. bilateral coplanarity zone applies to the exposed pad as well as the terminal. 4. radius on terminal is optional. 5. n is the total number of terminals. marking: yywwvzz. yy ww v zz @ last two digits of the manufacturing year manufacturing week plant identifier traceability code sublot identifier symbol min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 - 0.65 1.00 a3 0.20 ref l 0.30 0.40 0.50 0o - 14o b 0.18 0.25 0.30 d 5.00 bsc e 5.00 bsc e 0.50 bsc d1 4.75 bsc e1 4.75 bsc symbol min nom max d2 3.40 3.50 3.60 e2 3.40 3.50 3.60 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n32 www.ams.com revision 0.7 63 - 65 as8515 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 0.1 dec 16, 2011 zmo/mbr initial draft 0.2 jan 25, 2012 zmo updated table information on lin driver (page 24) pins 10, 11 updated in the file (pin assignments, figure 33 ) 0.3 mar 07, 2012 updated power dissipation info in absolute maximum ratings (page 7) 0.4 aug 14, 2012 updated table 14 , figure 33 . 0.5 nov 22, 2012 zmo/mbr updated operating conditions, electrical characteristics, ordering information, figure 12 . table 30 , table 32 , table 33 , table 45 . 0.6 mar 22, 2013 zmo table 1 and table 6 updated. 0.7 jul 26, 2013 updated table 30 , added figure 26 and notes to table 35 , modified table 30 , updated information in figure 26 . jul 31, 2013 mbr updated as8515 block diagram figure 1 . www.ams.com revision 0.7 64 - 65 as8515 datasheet - ordering information 12 ordering information the devices are available as the standard products shown in table 50 . note: all products are rohs compliant and ams green. buy our products or get free samples online at icdirect: http://www.ams.com/icdirect technical support is available at http://www.ams.com/technical-support for further information and requests, please contact us mailto: sales@ams.com or find your local distributor at http://www.ams.com/distributor table 50. ordering information ordering code description delivery form package AS8515-ZMFP data acquisition system with power management and lin transceiver tape & reel (5000 pcs) 32-pin mlf (5x5 mm) as8515-zmfm tape & reel (500 pcs) www.ams.com revision 0.7 65 - 65 as8515 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipien t or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact |
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